教育背景 

2015-02--2018-06   University of Lincoln   获博士学位 

2006-09--2008-12   中南大学   获硕士学位 

2002-09--2006-07   中南大学   获学士学位 

工作简历 

2021-04~现在, 中国科学院微电子所, 研究员 

2018-07~2021-04,中科院微电子研究所, 副研究员 

2010-10~2015-01,清华大学, 集成电路设计工程师 

高速串行接口SerDes 

1、50G多通道中长距串行接口PHY电路设计与实现关键技术研究, 课题负责人, 重点研发计划, 2019-08--2023-01 

2、面向新一代400GbE数据传输的超高速串行接口芯片关键技术研究, 项目负责人, 自然科学基金面上项目, 2021-01--2024-12 

3、高速 SerDes Tx 及无源信道 Bit-by-Bit 模块建模技术, 项目负责人, 横向, 2020-03--2021-03  

[1]    X. Zheng, H. Ding, F. Zhao, D. Wu, L. Zhou, J. Wu, F. Lv, J. Wang, X. Liu, “A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS, ” IEEE J. Solid-State Circuits (JSSC), vol. 55, no. 7 pp. 1864 - 1876, Jul. 2020. 

[2]   X. Zheng, F. Lv, L. Zhou, D. Wu, J. Wu, C. Zhang, W. Rhee, and X. Liu, “Frequency-domain modeling and analysis of injection-locked oscillators,” IEEE J. Solid-State Circuits (JSSC), vol. 55, no. 8, pp. 1651 - 1664, Jun. 2020. 

[3]      H. Wang, J. Peng, X. Zheng, and S. Yue, “A robust visual system for small target motion detection against cluttered moving backgrounds,” IEEE Trans. on Neural Networks and Learning Systems (TNNL), vol. 31, no. 3, pp. 839 - 853, March 2020. 

[4]    H. Ding, X. Zheng, D. Wu, L. Zhou, J. Wu, F. Lv, J. Wang, and X. Liu, “A 112-Gb/s PAM-4 transmitter with a 2-tap fractional-spaced FFE in 65-nm CMOS,” in Proc. IEEE European Solid-State Circuits Conf. (ESSCIRC), IEEE Solid-State Letters. (SSCL), vol. 2, no. 9, pp. 195-198, Sep. 2019.

[5]    X. Zheng, C. Zhang, and F. Lv et al., “A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 52, no. 11, pp. 2963-2978, Nov. 2017. 

[6]    X. Zheng, C. Zhang, and F. Lv et al.,“A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Apr. 2017. 

[7]   X. Zheng, F. Lv, and F. Zhao et al.,“A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Apr. 2017. 

[8]    X. Zheng, C. Zhang, and S. Yuan et al., “An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), Nov. 2016, pp. 85-88. 

[9]   X. Zheng, C. Zhang, and F. Lv et al., “A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS,” in Proc. IEEE European Solid-State Circuits Conf. (ESSCIRC), Sep. 2016, pp. 305-308. 

 2020年度中科院微电子研究所十佳先进工作者。